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| K6F2016U4D Family Document Title CMOS SRAM 128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 1.0 Initial Draft Finalized - Change for tWP : 55 to 50ns for 70ns product - Change for tWHZ : 25 to 20ns for 70ns product - Change for tDW : 20 to 25ns for 55ns product Draft Date January 6, 2000 May 4, 2000 Remark Preliminary Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 1.0 May 2000 K6F2016U4D Family FEATURES * * * * * * CMOS SRAM GENERAL DESCRIPTION The K6F2016U4D families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. 128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM Process Technology: Full CMOS Organization: 128K x16 bit Power Supply Voltage: 2.7~3.3V Low Data Retention Voltage: 1.5V(Min) Three state output status and TTL Compatible Package Type: 48-FBGA-6.00x7.00 PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) 0.5A Operating (ICC1, Max) 4mA PKG Type K6F2016U4D-F Industrial(-40~85C) 2.7~3.3V 551)/70ns 48-FBGA-6.00x7.00 1. The parameter is measured with 30pF test load. PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. A LB OE A0 A1 A2 DNU Vcc Vss B I/O9 UB A3 A4 CS I/O1 Row Addresses C I/O10 I/O11 A5 A6 I/O2 I/O3 Row select Memory array 1024 rows 128 x 16 columns D Vss I/O12 DNU A7 I/O4 Vcc E Vcc I/O13 DNU A16 I/O5 Vss I/O1~I/O8 Data cont Data cont Data cont I/O Circuit Column select F I/O15 I/O14 A14 A15 I/O6 I/O7 I/O9~I/O16 G I/O16 DNU A12 A13 WE I/O8 Column Addresses H DNU A8 A9 A10 A11 DNU 48-FBGA: Top View (Ball Down) Name CS OE WE A0~A16 Function Chip Select Input Output Enable Input Write Enable Input Address Inputs Name Vcc Vss UB LB DNU Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Do Not Use CS OE WE UB LB Control Logic I/O1~I/O16 Data Inputs/Outputs SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2Revision 1.0 May 2000 K6F2016U4D Family PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name K6F2016U4D-FF55 K6F2016U4D-FF70 Function CMOS SRAM 48-FBGA, 55ns, 3.0V 48-FBGA, 70ns, 3.0V FUNCTIONAL DESCRIPTION CS H X1) L L L L L L L L OE X 1) WE X 1) LB X 1) UB X 1) I/O1~8 High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9~16 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Active Active Active Active Active Active Active Active X1) H H L L L X 1) X1) H H H H H L L L H L X1) L H L L H L H X 1) L H L L H L L X1) X 1) 1. X means dont care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC + 0.5V -0.2 to 4.0V 1.0 -65 to 150 -40 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -3- Revision 1.0 May 2000 K6F2016U4D Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Note: 1. TA=-40 to 85C, otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CMOS SRAM Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.2 3) Typ 3.0 0 - Max 3.3 0 Vcc+0.22) 0.6 Unit V V V V CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply current Average operating current Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) Symbol ILI ILO ICC ICC1 ICC2 VOL VOH ISB ISB1 VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIH or VIL Cycle time=1s, 100%duty, IIO=0mA, CS0.2V, VIN0.2V or VINVCC-0.2V Test Conditions Min -1 -1 2.4 - Typ 0.5 Max 1 1 2 4 35 0.4 0.3 10 1) Unit A A mA mA mA V V mA A Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIH or VIL IOL = 2.1mA IOH = -1.0mA CS=VIH or LB=UB=VIH, Other inputs=VIH or VIL CSVcc-0.2V or LB=UBVcc-0.2V, CS0.2V, Other inputs=0~Vcc 1. Super low power product=3A with special handling -4- Revision 1.0 May 2000 K6F2016U4D Family AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=30pF+1TTL CMOS SRAM VTM3) R12) CL1) R22) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 1. The parameter is measured with 30pF test load. 55ns 1) 70ns Max 55 55 25 55 20 20 20 20 Min 70 10 10 5 0 0 0 10 70 60 0 60 60 50 0 0 30 0 5 Max 70 70 35 70 25 25 25 20 - Units tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 55 10 10 5 0 0 0 10 55 45 0 45 45 40 0 0 25 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CSVcc-0.2V 1) 1) Min 1.5 0 tRC Typ 0.5 - Max 3.3 22) - Unit V A ns Vcc= 1.5V, CSVcc-0.2V See data retention waveform 1. CSVcc-0.2V(CS controlled) or LB=UBVcc-0.2V, CS0.2V(LB, UB controlled). 2. Super low power product=1A with special handling. -5- Revision 1.0 May 2000 K6F2016U4D Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Data Valid tAA CMOS SRAM (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOH CS tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ Data out High-Z NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. -6- Revision 1.0 May 2000 K6F2016U4D Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH tWR(4) CMOS SRAM UB, LB High-Z TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) CS tAW tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z -7- Revision 1.0 May 2000 K6F2016U4D Family TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4) CMOS SRAM Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS or LB/UB controlled VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CSVCC-0.2V or LB=UBVcc-0.2V CS or LB/UB GND -8- Revision 1.0 May 2000 K6F2016U4D Family PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B 6 A #A1 B C D 5 4 B1 CMOS SRAM Unit: millimeters A1 INDEX MARK 0.50 0.50 3 2 1 C1 E C1/2 F G H B/2 Detail A A 0.25/Typ. Y 0.80/Typ. Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) -9- Side View D C Min A B B1 C C1 D E E1 E2 Y 5.90 6.90 0.30 0.20 - Typ 0.75 6.00 3.75 7.00 5.25 0.35 1.10 0.85 0.25 - Max 6.10 7.10 0.40 1.20 0.30 0.08 C Revision 1.0 May 2000 C 0.30 E1 E E2 |
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